a = '03, various modules
b = 'T11, DCT11
c = '21, KXT11-A
d = '23, KDF11-A
e = '23, KDF11-B
f = '73, KDJ11-A
g = '73, KDJ11-B
h = '04, KD11-D
i = '05/'10, KD11-B
j = '15/'20, KC11, KA11
k = '24, KDF11-UA
l = '34, KD11-E
m = '35/'40, KD11-A
n = '44, KD11-Z
o = '45/'50/'55, KD11-A, KD11-D
p = '60, KD11-K
q = '70, KB11-B, KB11-C
r = '84, KDJ11-B
s = VAX emulation

abcdefghijklmnopqrs

yyyyyyyyyyyyyyyyyyy	basic
yyyyyyynnnyynynyyyy	sob, sxt
yyyyyyyynnyyyyyyyyy	rtt
ynnyyyynnnyynynyyyn	mark
yyyyyyynnnyyyyyyyyy	xor
AnnyyyynnnyyByyyyyy	ash, ashc, mul, div
nnnCCyynnnCDnDEyEyn	46 floating-point instrs
nyyyyyynnnynnynnnyn	mfpt
yyyyyyynnnyynnnnnyn	mtps
nnnnnnnyyyyyyyyyyyy	KE11-A, -B available for mul, div, shift
FnnGGnnnnnGnnHnnnnn	CIS
nnnyyyynnnyyyyyyyyy	mfpi, mfpd, mtpi, mtpd
nnnnnyynnnnnnyynyyn	spl
nnnnnyynnnnnnynnnyn	csm

A = with KEV11 or KEV11-B
B = with KE11-E
C = with KEF11-A or FPF11
D = with FP11-A
E = FP11-B or FP11-C
F = limited subset (DIS) with KEV11-C
G = with KEF11-B
H = with KE44

111114411111144144N	opcodes 0100-0107, jmp to register
xxx1144xxx11144144N	opcode 0 in user or supervisor mode
hppoooohhhohhhhhhoN	opcode 0 in kernel mode
 11111111111111111N	opcodes 075040-075377, 075400-075777
111111111111111m11N	opcode 076600
u11FFff111FF1FFfFfN	opcodes 0170000-0177777
M11111111111111111N	opcodes 0210-0227
rrrrrrrr22rrrrrrrrr	jmp or jrs(?) mode 2, pc will get...

1 = T10 (trap through 010)
4 = T4
N = trap to native mode
x = not applicable
h = halt
p = Tpup+4 (?)
o = halt or T10
m = Med (?)
u = user microcode or T10
F = FPP or T10
f = FPP
M = maintenace instructions
r = register
2 = register + 2
  = ?

rRRRRRRrrRRrRrrRrRr	register as src, same reg in (r)+, @(r)+, -(r), @-(r), src is...
			(applies equally if reg is pc)

r = reg
R = reg +/- 2

000000000-000000000	V-bit action on swab instruction

AnnyyyynnnyyByyyyyy	EIS exists
 xx>>>>xxx>< <> >> 	if reg is odd and therefore 16-bit result produced, are
			condition codes based on 16 or 32 bit result?
			(< = 16, > = 32)

A = with KEV11
B = with KE11-E

AnnnnnnnnnnnBnnnnnn	FIS exists (floating instr set)
yxxxxxxxxxxxnxxxxxx	fmul and fdiv require one word of RB stack (whatever that is)
yxxxxxxxxxxxnxxxxxx	is interruptible
yxxxxxxxxxxxxxxxxxx	condition codes when interrupted are indeterminate
nyyyyyynnnynnynnnyn	mfpt exists
x443355xxx3xx1xxx5x	mfpt result (see mfpt in notes)

A = with KEV11
B = with KE11-F

nnnAAyynnnAnnnnynyn	FPP microcode
nnnBBCCnnnBDnEFGHyn	FPP hardware
xxxssaaxxxssxsIaIax	hardware FPP sync(s) async(a)
xxxJJnnxxxJnxnnnnnx	FPP instructions interruptible

A = with KEF11-A
B = with FPF11
C = with FPJ11
D = with FP11-A
E = with FP11-F
F = with FP11-B, FA11-C (FA11-C? with note I next line?)
G = with FP11-E
H = with FP11-B, FP11-C
I = FP11-B async, FP11-C sync
J = Y with KEF11-A, N with FPF11-A

yyyyyyynnnyynnnnnyN	mtps/mfps exists
yyyyyyyxxxy7xxxxxyx	user/supervisor mtps changes <3-0>
nnnnnnnxxxn7xxxxxnx	user/supervisor mtps changes <7-4>
yyyyyyyxxxy7xxxxxyx	user/supervisor mfps accesses <7-0>

N = psl affected only in native mode
7 = only if 777776 mapped

666A222666B8C2D822v	# of physical address bits

6 = 16
8 = 18
2 = 22
A = 16, 18, or 22
B = 18 or 22
C = 16, 18 with KT11-D
D = 16, 18 with KT11-C
v = various

111b88811162A4B244v	maximum physical memory (8K I/O page)

hex digit, 1 = 56, 2 = 248, 4 = 3840, 8 = 4088
A = 56, 248 with KT11-D
B = 56, 248 with KT11-C

yyyyyyyyyyyyyyyyyyy	kernel mode?
nnnnnyynnnnnnyAnyyn	supervisor mode?
nnnyyyynnnyyByAyyyn	user mode?
nnnnnyynnnnnnyynyyn	split I/D space
xxxkkkkxxxkkkkkkkkx	cm = 00 access mode
xxxuussxxxut sskssx	cm = 01 access mode [t=T250]
xxxuuttxxxut tt ttx	cm = 10 access mode [t=T250]
xxxuuuuxxxuuuuuuuux	cm = 11 access mode
xxx??uuxxx???????ux	mfpi, mfpd, mtdi, mtpd: which sp used for psw<13-12>=10? [?=unpredictable]
xxxyyssxxxysnsysssx	psw<15-12>, multiple sps, m[tf]p[di] exist w/wo mmu [yes, no, std]

A = Y with KT11-C
B = Y with KT11-D

xxxnnnnxxxnyyyyyynx	mmr0<08> implemented
xxxnnnnxxxnnnnynynx	mmr0<12> implemented
xxxyynnxxxynnnnnnnx	mmr1 implemented but always reads as 0
xxxnnyyxxxnnnyynyyx	mmr1 exists and works
xxxyyyyxxxyyyyyyyyx	mmr2 tracks instruction fetches
xxxnnnnxxxnnnnynynx	mmr2 tracks interrupt vectors
xxxnnyyxxxnnnyynyyx	mmr3<00-02> exist and function
xxxnnyyxxxnnnynnnyx	bit <03> (of mmr3, presumably) exists and functions
xxx yyyxxxynnynnyyx	bit <04> (of mmr3, presumably) exists and functions
xxxeeeexxxAnnynnyyx	bit <05> (of mmr3, presumably) exists and functions (e = exists only)

A = with KT24

xxx6666xxx62262266x	par width (bits: 2=12, 6=16)
xxxyynnxxxyooyooynx	can execute from par (o = 12-bits only)
xxxnnnnxxxnnnnynynx	bit <00> implemented
xxxnnnnxxxnnnnynynx	bit <07> implemented
xxxnnyyxxxnnnynnnyx	bit <15> implemented

14 444444444444444x	# of interrupt request levels
yyyyyyyyyyyyynyyyyx	does expected interrupt happen if psw<7-5> is lowered for only one inst?
yyyyyyyyynyyyyyyyyx	can intr handler be intrd before first instr?
nxxnnnnxxxnnnnnnnnn	are EIS instrs interruptible?
yxxxxxxxxxxxnxxxxxx	are FIS instrs interruptible?
 xxAAnnxxxAn nnnnnx	are FPP instrs interruptible? [A = Y with KEF11-A]
yxxyyxxxxxyxxyxxxxx	are CIS/DIS instrs interruptible?
nnnnnyynnnnnnyynyyn	does PIRQ (software interrupt request) exist?
xxxxxyyxxxxxxnyxyyx	is PIRQ cleared by reset?

nnnyyyynnnyyAyyyyyx	psw <15-12> mechanized [A = with KT11-D]
nnnnnyynnnnnnnynyyx	psw <11> mechanized
nnnyyyynnnynnynnnyx	psw <08> mechanized
ynnnnnnnnnnnnnnnnnx	psw priority is just high bit
nnnyyyyyyyyyyyyyyyn	psw accessible at 17777776
ynnyyyynnnyynnnnnyn	mtps/mfps instrs (bits <7-0> or <3-0>)
nnnnnyynnnnnnyynyyn	spl instr (bits <7-5>)
nnnnnnnyyynnnnnnnnn	can explicit psw ref set/clr t bit?
0000000011000000000	# instrs between rti setting t-bit and t trap
nyyyyyyyyyyyyynynyx	t-bit trap ends wait instr immediately
   yyyy y yyy n nyx	t-bit traps are taken before interrupts

1111122111111121221	# of sets r0-r5
111AB3311C322332331	# of stack pointers [A=3/2, B= /2, C=1/2: x/y = x, y useful]
nnnnnnnnynnnnnnnnnn	can execute out of registers?
nnnnnnnnynnnnnnnnnn	program can access registers at 17777700-17777717?
nnnnnnnyyynyyyyyynn	console can access registers at 17777700-17777717?
nnnnnyyyyynyyyyyyyy	odd address errors detected
xxxxxyynnnxnyny yyx	odd address trap on (r)+, @(r)+, -(r), @-(r), r will have been modified
ynnyyyyyyyyyyyyyyyy	bus timeouts detected by cpu
yxxyyyynyyynynyyyyx	bus error trap on (r)+, @(r)+, -(r), @-(r), r will have been modified
yxxyyyyyyyyynyyyynx	bus error while reading instructions using pc, pc will have been incremented
hnn4444hhh4h4h4444x	odd address or bus error while using (sp): [h=halt, n=no-error, 4=sp<-4/T4]
nnnyynnnnnynnnnnnnn	odd sp not detected

nnnyyyyyyyyyyyyyyyn	yellow-zone stack trap implemented?
xxxnnnnnnnnnAnyyynx	yellow stack trap programmable?  (Else fixed at 0400) [A = with KJ11]
xxxeeee44 e4eeeeeex	yellow trap action [e = execute then T4; 4 = T4]
xxxnnnnnnnnnynyyynx	separate redzone implemented?
xxxxxxxxxxxx4xs4sxx	redzone action [4=T4, s=sp<-4/T4]
