-*-TAGS-*-  File: macfiv, node: Top, Up: (macro)top * Menu: * Statement format:: * Operators:: * Single Operand:: * Double Operand:: Look here for common Single Operand and Double Operand instruction formats. * Flow of control:: Jumps, Branching, Subroutines, Traps and Interrupts * Byte Opcodes:: These operate on 8 bit quantities. * Floating Point:: ----------- Symbols: ~ is "NOT"; ^ is "AND" V is "OR"; DD- destination operand (d); SS- source operand (s).  File: macfiv, Node: statement format, Up: top, Next: Operators In accordance with DIGITAL's standard source program format, the following is the statement format: Label - begins in column 1 Operator - begins in column 9 Operand(s) - begin(s) in column 17 Comments(s) - begin(s) in column 33 However the above formatting conventions are not mandatory (free- field coding is permissible), but it is recommended that source programs be prepared in accordance with these conventions for consistency and clarity.  File: Macfiv, Node: Operators, Up: Top Prev: statement Format, Next: Single Operand SUMMARY OF OPERATORS Legal Unary Operators Unary Operator Explanation Example Effect + Plus sign +A Produces the positive value of A. - Minus sign -A Produces the negative (2's complement) value of A. Legal Binary Operators Binary Operator Explanation Example + Addition A + B - Subtraction A - B * Multiplication A * B (16-bit product returned) / Division A / B (16-bit product returned) & Logical AND A & B ! Logical inclusiive OR A ! B All binary operators have equal priority. items o terms can be grouped for evaluation within an expression by enclosing them within angle brackets. Terms so enclosed are evaluated first, and remaining operations are preformed from left to right, as shown in the examples below: .WORD 1+2*3 ;EQUALS 11(8). .WORD 1+<2*3> ;EQUALS 7(8).  File: Macfiv, Node: Single Operand, Up: Top, Prev: Operators, Next: Double Operand * Menu: * Common:: * Shifts:: * Rotates:: * Multiple Precision::  File: Macfiv, Node: Common, Up: Single Operand, Next: Shifts 0050DD CLR d clears d (d) <-- 0 0053DD DEC d decrements d (d) <-- (d) - 1 0052DD INC d increments d (d) <-- (d) + 1 0054DD NEG d negates d (d) <-- (d) (two's complement) 0051DD COM d complements d (d) <-- ~(d) (one's complement) 0057DD TST d tests d (d) <-- (d)  File: Macfiv, Node: Shifts, Up: Single Operand, Prev: Common, Next: Rotates 0062DD ASR d arith.shift right (d) <-- (d)/2 0063DD ASL d arith.shift left (d) <-- 2 * (d) 072000 ASH shift arithmetically 073000 ASHC arithmetic shift combined  File: Macfiv, Node: Rotates, Up: Single Operand, Prev: Shifts, Next: Multiple Precision 0003DD SWAB d swap bytes (d)low <---> (d)high 0060DD ROR d rotate right (d) <-- (d) shifted right 1 bit 0061DD ROL d rotate left (d) <-- (d) shifted left 1 bit  File: Macfiv, Node: Multiple Precision, Up: Single Operand, Prev: Shifts, 0055DD ADC d add carry (d) <-- (d) + c 0056DD SBC d subtract carry (d) <-- (d) - c adc sbc sxt   File: Macfiv, Node: Double Operand, Up: Top, Prev: Single Operand, Next: Flow of Control * Menu: * General:: Things like: MOV, ADD, CMP, etc. * Register Destination:: MUL, DIV, XOR * Bit, * Logical:: These set bits, clear them, and test them  File: macfiv, Node: General, Up: Double Operand Next: Register Destination 02SSDD CMP s,d compare form(s) - (d) 06SSDD ADD s,d add (d) <-- (s) + (d) 16SSDD SUB s,d subtract (d) <-- (d) - (s) 01SSDD MOV s,d move (d) <-- (s)  File: macfiv, Node: Register Destination, Up: Double Operand, Prev: General, Next: Logical 070000 MUL s,r multiply source by Reg -> reg, reg[1] 071000 DIV divide R,R[1] by S -> R (remainder in R[1]) 074000 XOR exclusive OR  File: macfiv, Node: Logical, Up: Double Operand Prev: Register Destination 03SSDD BIT s,d bit test form (s) ^ (d) 04SSDD BIC s,d bit clear (d) <-- [~(s)] ^ (d) 05SSDD BIS s,d bit set (d) <-- (s) V (d)  File: Macfiv, Node: Flow of control, Up: Top, Prev: Double Operand, Next: Byte Opcodes * Menu: * Condition Code Operators:: * Branching Instructions:: * Subroutines:: * Traps and Interrupts::   File: Macfiv, Node: Condition Code Operators, Up: Flow of Control, Next: Branching Instructions Machine Code Mnemonic Meaning 000241 CLC clear C 000242 CLV clear V 000244 CLZ clear Z 000250 CLN clear N 000257 CCC clear C,V,Z,N 000261 SEC set C 000262 SEV set V 000264 SEZ set Z 000270 SEN set N 000277 SCC set C,V,Z,N PSR (Processor Status Register) C ('Carry' - bit 0) 1: if addition resulted in carry from MSB 0:otherwise V ('Overflow'- bit 1) 1: if added numbers are of same sign and their sum is of the opposite sign. 0:otherwise Z ('Z code'- bit 2) 1: if result of last instruction was zero. 0:if result of last instruction <> 0. N ('N code'- bit 3) 1: if result of last instruction was < 0. 0:if result of last instruction was >= 0.  File: Macfiv, Node: Branching Instructions, Up: Flow of control Prev: Condition Code Operators Next: Subroutines There is only one Unconditional Branch. It is called BR. all the other BR instructions test the condition codes, and and branch if the conditions specified below are set. Machine Code Mnemonic Branch to 'a' if 000400 BR a (unconditionally) 001000 BNE a not equal to 0 (Z=0) 001400 BEQ a equal to 0 (Z=1) 002000 BGE a greater than or equal to 0 [signed] 002400 BLT a less than 0 [signed] 003000 BGT a greater than 0 [signed] 003400 BLE a less than or equal to 0 [signed] 100000 BPL a plus (N=0) 100400 BMI a minus (N=1) 101000 BHI a higher [unsigned] 101400 BLOS a lower or same [unsigned] 102000 BVC a overflow clear (V=0) 102400 BVS a overflow set (V=1) 103000 BCC a carry clear (C=0) 103000 BHIS a higher or same (C=0) [unsigned] 103400 BLO a lower (C=1) [unsigned] 103400 BCS a carry set (C=1)  File: macfiv, Node: Subroutines, Up: Flow of control Prev: Branching Instructions, Next: Traps and Interrupts 000200 RTS return from subroutine 000207 RETURN return from subroutine (RST PC) 000240 NOP (no operation) jump to subroutine at d 004700 CALL jump to subroutine (JSR PC,xxx) 006400 MARK mark  File: macfiv, Node: Traps and Interrupts, Up: Flow of Control, Prev: Subroutines 000000 HALT halt Halt is included here because an attempt to use it by a non privileged RSTS/E user is trapped by the system. 000001 WAIT wait for interrupt 000002 RTI return from interrupt 000003 BPT breakpoint trap 000004 IOT input/output trap 000005 RESET reset external bus 000006 RTT return from interrupt 104000 EMT emulator trap 104400 TRAP trap  File: Macfiv, Node: Byte opcodes, Up: TOP Prev: Flow of Control, Next: Floating Point Machine Code Mnemonic Meaning 105000 CLRB clear (byte) 105100 COMB complement (byte) 105200 INCB increment (byte) 105300 DECB decrement (byte) 105400 NEGB negate (byte) 105500 ADCB add carry (byte) 105600 SBCB subtract carry (byte) 105700 TSTB test (byte) 106000 RORB rotate right (byte) 106100 ROLB rotate left (byte) 106200 ASRB arith. shift:r (byte) 106300 ASLB arith. shift:l (byte) 110000 MOVB move (byte) 120000 CMPB compare (byte) 130000 BITB bit test (byte) 140000 BICB bit clear (byte) 150000 BISB bit set (byte)  File: Macfiv, Node: Floating Point, Up: top Prev: Byte Opcodes Machine Code Mnemonic Meaning 075000 FADD floating add 075010 FSUB floating subtract 075020 FMUL floating multiply 075030 FDIV floating divide 170600 ABSD Make absolute double 170600 ABSF Make absolute floating 172000 ADDD Add double 172000 ADDF Add floating 170000 CFCC Copy floating condition codes 170400 CLRD Clear double 170400 CLRF Clear floating 173400 CMPD Compare double 173400 CMPF Compare floating 174400 DIVD Divide double 174400 DIVF Divide floating 177000 LDCDF Load and convert from double to floating 177000 LDCFD Load and convert from floating to double 177000 LDCID Load and convert integer to double 177000 LDCIF Load and convert integer to floating 177000 LDCLD Load and convert long integer to double 177000 LDCLF Load and convert long integer to floating 172400 LDD Load double 176400 LDEXP Load exponent 172400 LDF Load floating 170100 LDFPS Load FPPs program status 106500 MFPD Move from previous data space 171400 MODD Multiply and integerize double 171400 MODF Multiply and integerize floating 106600 MTPD Move to previous data space 171000 MULD Multiply double 171000 MULF Multiply floating 170700 NEGD Negate double 170700 NEGF Negate floating 170011 SETD Set double mode 170001 SETF Set floating mode 170002 SETI Set integer mode 170012 SETL Set long integer mode 000230 SPL Set priority level 176000 STCDF Store and convert from double to floating 175400 STCDI Store and convert from double to integer 175400 STCDL Store and convert from double to long integer 176000 STCFD Store and convert from floating to double 175400 STCFI Store and convert from floating to integer TAGS: :SGAT Top:15 statement format:497 Operators:1074 Single Operand:2108 Common:2273 Shifts:2652 Rotates:2916 Multiple Precision:3191 Double Operand:3390 General:3657 Register Destination:3924 Logical:4171 Flow of control:4408 Condition Code Operators:4620 Branching Instructions:5482 Subroutines:6502 Traps and Interrupts:6847 Byte opcodes:7348 Floating Point:8074