What is the complex in my 8590/95 or 9590/9595?  Look HERE

Type 0   Type 1 (G-K)   Type 2 (H-L)   Type 3 (M)   Type 4 (N-Y)

Useless Trivia
16 Bit Busmasters
Will a -xxx Complex work in my 90 / 95?
 

Replacing CPUs on a Complex
Check the Pin 1 orientation before powering up! I burnt a good 486DX4-75 ODPR  (smoke! Popping noises!) after not checking my pin 1 placement! 

OK, crankheads, here's a unscientific comparison of some complex performances. Some unusual results...

Processor Complex
   In the first PS/2* models, most components were integrated into the planar of the system. This severely limited upgrade options and upgrade flexibility. While one component was upgraded, for example the processor, the other components such as the I/O controller and the memory controller were not. This created combinations of fast and slow components, which created unbalanced systems. Unbalanced systems are not as efficient as balanced systems where every components¢ performance is matched against other components¢ performances.
   With this in mind, the server key components have been grouped together on a separate card known as a processor complex. Now the processor is contained on a removable processor complex board, which also holds the processor/memory bus, the memory controller, DMA controller, and Micro Channel* bus interface. Placing the processor on a complex together with key components means that when a system is upgraded, balanced systems performance can be maintained.
   IBM has provided an upgrade path for existing and future file servers that allows network design engineers to replace the system processor complex with a faster and more efficient system processor complex at a later date. This policy of upgrading allows the server to accommodate increased server CPU utilization without the need to buy a complete new machine.
Within the processor complex there are many features that are capable of providing more efficient data transfer. They consist of:
· Cache
· Dual Path to Memory
· Two-Way Interleaved Memory Banks
· 32-bit DMA Controller
· 40MBps Data Streaming

Processor Cache
   Processor cache is a memory that can be accessed 5 to 10 times faster than standard memory. Cache memory uses Static Random Access Memory (SRAM) which is much faster than the Dynamic Random Access Memory (DRAM) used for system memory. SRAM is more expensive and requires more power, which is why it is not used for all memory.
   There are two levels of cache. The cache incorporated into the main system processor is known as Level 1 (L1) cache. The 486 incorporates a single 8KB cache (Overdrive chips can have 16KB). Pentium** features two 8KB caches, one for instructions and one for data. These caches act as temporary storage places for instructions and data obtained from slower, main memory. When a system uses data, it will be likely to use it again, and getting it from an on-chip cache is much faster than getting it from main memory.
   The second level of cache, called second-level cache or Level 2 cache, provides additional high speed memory to the Level 1 cache. This additional cache memory works together with the cache memory native to the main processor (L1). If the processor cannot find what it needs in the processor cache (a first-level cache miss), it then looks in the additional cache memory. If it finds the code or data there (a second-level cache hit), the processor will use it, and continue. If the data is in neither of the caches, an access to planar memory must occur. (G, H, and L complexes do NOT have L2 cache, nor do they have a cache socket).

Within Level 2 cache there also two possible types of caching:
1. Write-Through Cache
Read operations are issued from the cache but write operations are sent directly to the standard memory. Performance improvements are obtained only for read operations.
2. Write-Back Cache
Write operations are also done to the cache. Transfer to standard memory is done if:
· Memory is needed in the cache for another operation
· Modified data in the cache is needed for another application
It is believed that OS/2 uses much wider memory area than DOS or Microsoft Windows**, so write-back cache is sometimes worse than write-through cache mode.
Ed. I thought that all complexes are set to write-through...

Dual Path to Memory
   When bus masters were implemented on Micro Channel servers, it was found that there was often contention for memory access between the processor and the bus masters, and that the processor was being delayed waiting for bus masters to release the path into memory. The new design of the processor complexes addresses these issues by providing a dual-path into memory, effectively providing two paths to system memory, one from the processor and one from the Micro Channel.
These two separate paths to system memory allow overlapping of processor and bus master cycles. (M-Y complexes)

Three kinds of overlapped cycles can occur: 
· Processor reads to Level 2 cache simultaneously with bus master I/O 
· Processor reads to Level 2 cache simultaneously with bus master memory access
· Processor reads to memory simultaneously with bus master I/O
   In addition, both processor and Micro Channel cycles are buffered into 16 bytes blocks, further alleviating the contention for memory by reducing the frequency of the accesses. Implementing dual-path access to memory and the buffering of cycles can give a system throughput of up to three times that of a server without it.

Two-Way Interleaved Memory Banks
   Another performance advantage is gained when the processor is accessing memory in burst mode. Memory is split into two banks, and data or code is stored sequentially across these banks; for example addresses 0 and 2 are held in bank 1, and addresses 1 and 3 are held in bank 2. The reason for this arrangement is that when a 486 burst mode request is made, the accesses to memory will be sequential. When the memory controller detects such a burst request from, for example, bank 0, it also pre-fetches the next 32 bits of data from bank 1. This way, the processor is not kept waiting while the information is being retrieved from memory.

32-bit DMA Controller
A Direct Memory Access (DMA) controller is a dedicated unit with the ability to move data between system memory and a device on the Micro Channel. It is used by simple adapters, and also by the parallel and serial ports. Earlier versions of the PS/2 Model 95 (G-L complexes) implemented a 24-bit DMA, limiting DMA memory transfers to below 16MB (whereas the 486 processor was able to address up to 4GB of memory). On 32-bit systems with more than 16MB of memory, this could cause problems if a DMA access was for memory above 16MB. The operating system could work around the problem by ensuring that DMA buffers were always below 16MB when a DMA transfer was done, but this imposes a performance penalty.

40MBps Data Streaming
The 40MBps data streaming transfer (M through Y complexes) offers considerably improved I/O performance. As in many cases, blocks transferred to and from memory are stored in sequential addresses, so repeatedly sending the address for each four bytes is unnecessary. With data streaming transfer the initial address is sent, then the blocks of data are sent and it is then assumed that the data requests are sequential.

16 Bit Busmasters
     The 9595 used with 16-bit busmasters (for example, the PS/2 Micro Channel SCSI Adapter (#1005, 6451109)) that support 32-bits of addressing will cause system malfunction or potential loss of data when the user installs greater than 16MB of system memory.

Complexes work in all 8590 / 8595 / 9590 / 9595 / 500
Any existing Model 90, Model 95, or PC Server 500 can be upgraded to a new Processor Complex. For example, Base 1 to Base 2 or Base 3 or Base 4; Base 2 to Base 4, etc.

NOTE: The power supply in the Model 90 case is supposedly a little small for the DX50, P60, P66, and P90 complexes. And in addition, the air baffle in the Model 90 may have to be removed if a processor with a big heat sink or heatsink / fan combination is installed. BUT I have to wonder- it's rated for 215 Watts, it isn't THAT small..Hell, the 9577 PS is only 194 Watts.

95A Planar Lacks Backward Compatability
   The 95A (dual serial/dual parallel) planar will NOT support other than a Type 4 complex. End of story. You will get a 174 error and nothing more.

More Useless Trivia
Hi Louis !
 >Peter, what are the differences in the G, J, K, and M class boards?

Obviously not only the speed ...
   As far as I can see IBM followed different "evolutionary stages" with these boards. The first being presented was the 33MHz Type 1 (64F0198), which was offered as 64F0201 with only 25MHz almost at the same time. The 33MHz model had been the "top line" model with cache and all that. I got a "handwired" platform from Charles Lassiter, which has still 64F0198 printed on the *card* but a 25.00Mhz oscillator and "handstamped" ASICs. Looks a lot like a pre-production sample - and prooves that the 25MHz is derived from the 33MHz - not other way round. The earliest HRM for the 95 however (dated March 1990 IIRC) mentiones both of them.
   Mentions "optional 256K cache" - which makes clear that no other board than 64F0198 and 64F0210 is meant. The 486DX2-33/66 board 92F0145 is then a much later developement out of the Non-SOD 64F0198 - intended to use Flash-BIOS, but not fully developed or supported. (That's the board with the odd bank-select jumper in the top/right corner)
   (Ed. edit based on personal inspection of a 92F0048) The 92F0048  appears to be also based on the Non-SOD 64F0198, with a DX50 cpu, a 50MHz oscillator, and some decoding circuitry mounted in the area that on the SOD would go on. The matching 12nS cache module is 92F0050.
   The smaller type-1 platforms had been offered to form "entry models" - focussed on the Mod. 90 (92F0065 - 486SX-20 and 92F0049 - 486DX-20). The 92F0065, which I call "Kiddies CPUs", is the only one which has a  487SX-presence" Jumper. 
   A totally different thread are the Type-2 platforms, which all base on the 92F0079. The type-2 platforms have been developed to make memory selection a bit easier - for the cost of some performance as a cost-efficient solution.
   The type-3 platform of the -M- class has been intended for high-end servers: paired memory *and* ECC support. Only few Mod. 90 saw this platform as far as I know. Don't know if IBM ever offered it officially in  the 90. I remember having seen 2 or 3 Mod. 9590-AMF at a customer - but they had the [PA]-sticker close to the Serial-number decal ... which identifies them as "upgraded machines".
   The -M- platform even survived the change from the 8595 to the 9595 (with the old planar and LED-planel however) along with the 92F0161 486DX2-25/50 -L- platform. Strange enough.
   The final stage of the 486-line was reached with the Type-4 -N- class board 61G2343 - which was the precessor to the 5V-Pentium (P5) platform. This however is a totally new developement, at a time when 486 processors were already a bit dusted.
   The Type-4 platforms are all very similar with the integrated Intel Cache chipset. I think there has been a lot experience used from the -M- class DX-50 board. But this time everything fits on *one* printboard and make the funny shielded hi-density connectors obsolete for the "second
floor" printboard.

>Are there any ECAs related to any specific FRUs?
   No. The "classical" -K-type board went through several "technical  changes without notice" and that was all (S.O.D. - still unclear which chip should fit in there ...).
   So did the "92F0079-family" Type-2 boards. IBM never announced any technical changes on these boards. As far as I can recall there was no common ECA at anytime on any of the processorboard. Only "withdrawn from marketing" notices ...
   There had been some traffic on the IBM BBS in 1991 - 1993 when people found out that they could not use over 1GB harddisks with the Type 1 & 2 platforms, but IBM offered the upgrade Eproms (for free !) until the deadline of December 1992, which was then stretched out to December 1993 at last.

Unsorted Oorts
       When installed with the 486SX/25 Processor Upgrade Option, 16-bit bus masters (for example, PS/2 Micro Channel SCSI Adapter (#1005, 6451109)) that support 32-bits of addressing will cause system malfunction and/or potential loss of data when the user installs greater than 16MB of system memory.

RESOLUTION  This issue is resolved by the following updated file(s) for Windows 95 and OSR2, and later versions of these file(s): HIMEM.SYS  ver 3.95  dated 10/2/95  33,127 bytes 
  This and later versions of HIMEM.SYS support the API used by the computers listed in this article for reporting memory in excess of 16 MB. 

STATUS   Microsoft has confirmed this to be a problem in Microsoft Windows 95. An update to address this problem is now available, but is not fully regression tested and should be applied only to computers experiencing this specific problem. Unless you are severely impacted by this specific problem, Microsoft does notrecommend implementing this update at this time. Contact Microsoft Technical Support for additionalinformation about the availability of this update. 
  This issue is resolved in Microsoft Windows 98. 

MORE INFORMATION   The computers listed in this article use INT 15 ax=c700h to report memory above 16 MB. (Other IBM PS/2 Microchannel computers may use INT 15 ax=E881.) The updated version of Himem.sys accepts a /P switch that causes HIMEM to use this API to detect memory in excess of 16 MB. Without the /P switch, the updated HIMEM does not use this API, and functions the same as the shipping version of HIMEM. 

  The new version of Himem.sys reports itself as version 3.95, the same as the shipping version.
Knowledge Base Reference Article: Q137755: No More Than 16 MB of Memory Reported on IBM PS/2 Model 77, 90

Sorry, I can't find it on M$. email ME for a copy of HIMEMUPD.EXE