8590 / 9590
8595, 9595-xLx, xMx
9585, 50 pin SCSI
9585, 68 pin SCSI
  ECC-P Memory for all 9585 Models
9595A (Dual Serial/Parallel)
Planar ADF decyphering (it's a start...)

Microchannel "Stages"
(Historical Information Footnote: The IBM never called its MCA "Stage x" or so. This was an informal technicians method to define about which stage of implementation we were talking at all. Here's what is what.
- MCA Stage 1 was the 16-bit "Local Bus" (hehe) version which can be found in Mod. 50 and 60 with the 80286. Bus and CPU run at 10MHz - therefore the odd Local-Bus-joke. 
- MCA Stage 2 was the 32-bit variation as used in the Mod. 70 and 80.
Introduction of "Matched Memory Cycles" for better memory performance.
- MCA Stage 3 came with the Mod. 90 / 95 and "Bermuda" 76 / 77. Same as S-3 but doubled speed. Capable to run data at 40MB/s in 64-bit burst mode. Matched Memory not suppported on this stage.
- MCA Stage 4 is that of the Server 9595A, 500 and -partially- the "Lacuna" 76 / 77. Basically a Stage 4 with optimised protocols. It supports the "Synchro-Stream" architecture with up to 80MB/s at 64-bit burst access. The adapters communication protocol works asynchronous - the data transfer after negotiation in synchronous burst mode. Concepted was 160MB/s in a 128-bit mode but as far as I know not realized. Not even the Pentium 90 platform supports this mode.
- MCAStage 5 should have been developed for the RS/6000 with the PowerPC chipset and should have supported full 128-bit access. Project has been "stabilized" before announcement. Which means: it was dead.)