The Modules

Cypress-SPARC MBus Modules

Footnotes:

1.

Yes indeed! A SPARCstation-2 CPU and FPU (together with an physically-tagged/virtually-indexed cache controller) on an MBus module! This requires explicit PROM and O/S support, and probably works in relatively few systems, and possibly only under SunOS 4.x (and derivatives). The SPARCstation-10 PROM correctly identifies both the CPU and cache-controller, but when stock Solaris starts to boot, it fails to access SBus devices (including the boot disk) and hard hangs. Perhaps these modules depend on the exact bus-timing characteristics of the SS600 memory-controller?

2.

Solaris 2.x runs in single-processor mode when this module is present, although SunOS 4.x can cope with MP on these modules.

3.

Solaris 2.x runs in single-processor mode when early revisions (pre -08) of this module is present, although SunOS 4.x can cope with MP on these modules.

4.

Unfortunately there are two very different parts with the Sun 501-1301 designation: the single-CPU module has only three circular heatsinks (one on the CPU, FPU and cache-controller, respectively), whereas the dual-CPU "SM100" modules have six circular heatsinks.

SuperSPARC MBus Modules

All SuperSPARC-based modules with more than one CPU are double-width cards.

Some of the module types come in several revision levels. When using multiple modules per MBus/XBus, safest practice is to ensure the modules are identical (same part numbers). For instance, mixing 501-2571 (SM61) with 501-2613 (also SM61) will cause trouble on a 50MHz MBus. See if you can find out why, using the table below.

Guidelines for mixed-type and mixed-revision configurations are discussed in General Module Configuration Rules.

Sun made a historical mess of naming the various types of dual-CPU SuperSPARC modules, see The SM52 Name Game.

Beware of vendors of "SM41" modules that will not disclose the part-number in advance: they may be trying to offload a 501-2318, which will not work in the vast majority of systems.

WARNING:  it has recently come to light that some SM41, SM51 and maybe SM71 modules appear to be specific to the Fujitsu Teamserver, and do not work in other systems. Unfortunately there is no known way to distinguish these Fujitsu-custom modules from "regular" ones, as both have the same "501-" part-number stickers. If you have any information on how to distinguish these modules, please email spooferman@excite.com .

Colloquial Type	Part Number	No. CPUs	CPU	CPU MHz	Cache Controller(s)	Ext. Level-2 Cache per CPU	Max. MBus Speed (MHz)	Max. XBus Speed (MHz)	Notes
SM20	501-2214 501-2218	1	SuperSPARC-I 2.x	upto 33	none	none	upto 33	n/a	1
SM21	501-2216	1	SuperSPARC-I 1.x	33?	MXCC	1Mb	less than 33?	33?	2
SM30	501-1889 501-2215 501-2239	1	SuperSPARC-I 2.x	upto 36	none	none	upto 36	n/a	1
SM40	501-2219 501-2295	1	SuperSPARC-I 2.x	upto 40	none	none	upto 40	n/a	1
	501-2358	1	SuperSPARC-I 3.0-3.3	upto 40	none	none	upto 40	n/a
	501-2570	1	SuperSPARC-I 3.5	upto 40	none	none	upto 40	n/a
SM41	501-2318	1	SuperSPARC-I 2.x	40.3	MXCC 1.x	1 Mb	less than 33	33	3
	501-1714	1	SuperSPARC-I 2.x	40.3	MXCC	1 Mb	40	40
	501-2258 501-2359	1	SuperSPARC-I 2.x	40.3	MXCC 1.x	1 Mb	40	40
	501-2270	1	SuperSPARC-I 2.x	40.3	MXCC 1.x & 2.x	1 Mb	40	40
SM52	501-2043	2	SuperSPARC-I 2.x	45	MXCC	1 Mb	40	n/a	5, 8
SM50	501-2568 501-2712	1	SuperSPARC-I	upto 50	none	none	50	n/a
	501-2528	1	SuperSPARC-I 3.5	upto 50	none	none	50	n/a
	501-2708	1	SuperSPARC-I 5.x	upto 50	none	none	50	n/a
SM51	501-2317	1	SuperSPARC-I	50	MXCC	1 Mb	40	50
	501-2352 501-2360 501-2361 501-2387	1	SuperSPARC-I 3.0-3.3	50	MXCC 2.x	1 Mb	40	50
	501-2562 501-2607	1	SuperSPARC-I 3.5	50	MXCC 2.x	1 Mb	40	50
	501-2617	1	SuperSPARC-I 5.x	50	MXCC 3.1	1 Mb	40	50
	501-2707	1	SuperSPARC-I 5.x	50	MXCC 2.x	1 Mb	40	50
	501-2754	1	SuperSPARC-I 5.2	50	MXCC 3.3	1 Mb	40	50
SM51-2	501-2353	1	SuperSPARC-I 3.0-3.3	50	MXCC 2.x	2 Mb	40	40	4, 8
	501-2601	1	SuperSPARC-I 3.5	50	MXCC 2.x	2 Mb	40	40
	501-2618	1	SuperSPARC-I 5.x	50	MXCC 3.x	2 Mb	40	40
	501-2755	1	SuperSPARC-I 5.2	50	MXCC 3.3	2 Mb	40	40
SM52X aka SM512	501-2431	2	SuperSPARC-I 3.0-3.3	50	MXCC 2.x	1 Mb	40	n/a?	8
	501-2609	2	SuperSPARC-I 3.5	50	MXCC 2.x	1 Mb	40	n/a?
	501-2756	2	SuperSPARC-I 5.2	50	MXCC 3.3	1 Mb	40	n/a?
	501-2780	2	SuperSPARC-I 5.1	50	MXCC 3.1	1 Mb	40	n/a?
SM520	501-2444	2	SuperSPARC-I rev 3.0-3.3	50	MXCC	1 Mb	40	n/a?	8
SM521	501-2445	2	SuperSPARC-I rev 3.0-3.3	50	MXCC	1 Mb	40	n/a?	6
SM61	501-2571	1	SuperSPARC-I 3.0-3.3	60	MXCC 2.x	1 Mb	40	40	9
	501-2519	1	SuperSPARC-I 5.x	60	MXCC 3.x	1 Mb	50	50
	501-2613	1	SuperSPARC-I 5.x	60	MXCC 2.x	1 Mb	50	50
	501-2752 501-2825	1	SuperSPARC-I 5.2	60	MXCC 3.3	1 Mb	50	50
	501-2769	1	SuperSPARC-I 5.x	60	MXCC 3.1	1 Mb	50	50
	501-2772	1	SuperSPARC-I	60	MXCC	1 Mb	50	50
	501-2782	1	SuperSPARC-I 5.x	60	MXCC 2.0	1 Mb	50	50
SM61-2	501-2543	1	SuperSPARC-I 5.x	60	MXCC 3.1, 3.2 & 3.3	2 Mb	50	55	4
	501-2757	1	SuperSPARC-I 5.2	60	MXCC 3.1, 3.2 & 3.3	2 Mb	50	55
SM71	501-2520	1	SuperSPARC-II 1.6	75	MXCC 3.3	1 Mb	50	50
	501-2904	1	SuperSPARC-II 2.3	75	MXCC 3.3	1 Mb	50	50
	501-2925	1	SuperSPARC-II 2.4.5	75	MXCC 4.5	1 Mb	50	50
	501-2940	1	SuperSPARC-II 2.4	75	MXCC 3.3	1 Mb	50	50
	501-3001	1	SuperSPARC-II 2.4.3	75	MXCC 3.3	1 Mb	50	50
	501-4130	1	SuperSPARC-II 2.4.5	75	MXCC 3.3	1 Mb	50	50
SM81	501-2953 501-4810	1	SuperSPARC-II 2.4.5	85	MXCC 4.5	1 Mb	50	50
	501-3033	1	SuperSPARC-II 2.4.5	85	MXCC 4.4	1 Mb	50	50
SM81-2	501-3022	1	SuperSPARC-II 2.4.3	85	MXCC 4.4	2 Mb	50	50	4
	501-3098 501-4780 501-5056	1	SuperSPARC-II 2.4.5	85	MXCC 4.5	2 Mb	50	50
SM91-2	501-2818	1	SuperSPARC-II 2.4.x	90	MXCC 4.x	2 Mb	50	50	4, 10

Footnotes:

1.

Maximum of 1 such module per MBus: these modules did not properly adhere to the MBus Level 2 (multiprocessor) protocol.

2.

Not shipped in Sun retail products - these modules were used in some early OEM clones of the SPARCstation-10.

3.

Intended only for those few early SPARCcenter-2000 systems that were fitted with 66MHz control-boards: 501-2318 modules are designed for system-bus interface speeds only upto 33MHz.

4.

Only multi-XDBus systems such as the SPARCcenter-2000 or Cray CS6400 can utilise the 2nd Mb of external cache: in other systems, these modules behave as if they had only 1 Mb of external cache.

5.

Very rare; announced for the SPARCstation-10 in 1994, and customer orders taken, but withdrawn due to heat (and possibly yield) problems; shipped by Sun in some SPARCcluster systems.

6.

Mirror-image of SM520, physically fits in only the SPARCserver-600 series, in the second MBus slot.

7.

This note intentionally left blank.

8.

There is a lot of public confusion regarding the colloquial names of the various dual-SuperSPARC modules, mainly due to the fact that Sun changed the naming-scheme along the way. The official Sun Spares listings and Field Engineers Handbook contradict both each other and themselves, which hardly helps. See The SM52 Name Game.

9.

Although counter-intuitive, these particuler modules really do have a maximum MBus and XBus speed of only 40MHz.

10.

Very rare; installation instructions for the SPARCserver-1000 were published by Sun.

.

HyperSPARC MBus Modules

Even original manufacturer Ross never had a complete unambiguous naming scheme - the same modules had different names depending on whether they were shipped as upgrades or factory-fitted. In the upgrade case, identical modules would have a name dependant on the type of system the upgrade kit was intended for: SS10 versus SS20 versus SS600 (the single-module 72MHz upgrade kits for SS10 and SS600 contained different BootPROMs and installation instructions, but identical MBus modules).

In a couple of cases, Ross even renamed module-types during production...sheesh!

To make matters worse, in 1997, Ross started labelling modules with generic ("it's a HyperSPARC module of some kind") 370-series part numbers in place of the original descriptive ("it's a dual-125MHz HyperSPARC module with 256Kb cache per CPU") 511-series part numbers. Bridgepoint Technical Manufacturing, who obtained the rights to the HyperSPARC designs and inventory in 1998, relabelled some of the old (1995-1996) module inventory they obtained in 1998, with generic 370-series labels. More recently, Bridgepoint appear to have changed to a generic 511- numbering scheme (all modules with RT626 are "511-6226")???

I have thus (reluctantly) adopted my own canonical module-type-descriptive naming scheme here.

HM s n - c 
   | |   |
   | |   |
   | |   external cache size per CPU, in Kb
   | |
   | S = single CPU
   | D = dual CPU (single-width module)
   | W = dual CPU (double-width module)
   |
   CPU speed,
      either:
         the CPU clock-speed in MHz
         (PLL-clocked modules only)
      or:
         an x followed by the MBus->CPU clock-multiplier
         (bus-clocked modules only)

There is also plenty of confusion about the difference between chip- and module-names (eg: the SS10 and SS20 PROM banner displays approximate CMTU chip names rather than CPU or module names). See HyperSPARC Chips.

The following table of HyperSPARC modules is not necessarily exhaustive. Other module types just might exist, such as modules with only 128 Kb external cache, or dual-CPU 80Mhz modules, etc. etc.

In some cases, the supported MBus speeds for each module-type may depend on the module revision-level. In the table below, listed MBus speeds are known to be supported by some (but not necessarily all) revisions of a given module-type.

Note also that although the modules themselves may operate properly on a high-speed MBus (eg: 75, 70 or 66Mhz), individual systems MBus implementations may not run reliably at such speeds - see Ross HS30 for commentary.

Also, the different revisions of some module-types have considerably different overheating risks.

All single-CPU HyperSPARC modules are single-width. Some dual-CPU modules are double-width, sometimes depending on revision. In the table below, modules that are known to be double-width are so marked, but beware that some of the others may be wide too.

Any ex-Ross employees that can shed any light on the functional, width, or heat differences between module revisions, please contact spooferman@excite.com. Even a chronology of releases would help.

Module Type	No. CPUs	CPU type	CPU MHz	Cache Controller type	Ext. Level-2 Cache per CPU	Max. MBus Speed (MHz)	Notes
HMx1S-256	1	RT620A	40	RT625	256 Kb	40	3
HM55S-256	1	RT620A	55	RT625	256 Kb	40
HM55D-256	2	RT620A	55	RT625	256 Kb	40
HM66S-256	1	RT620A	66	RT625	256 Kb	50
HM66D-256	2	RT620A	66	RT625	256 Kb	50
HM72S-256	1	RT620A	72	RT625	256 Kb	50
HM72D-256	2	RT620A	72	RT625	256 Kb	50
HM80S-256	1	RT620A?	80	RT625	256 Kb	50
HM90S-256	1	RT620B	90	RT625	256 Kb	50
HM90D-256	2	RT620A	90	RT625	256 Kb	50	16
HM90D-256	2	RT620B	90	RT625	256 Kb	50	16
HM100S-256	1	RT620B	100	RT625	256 Kb	50	4
HM100D-256	2	RT620B	100	RT625	256 Kb	50	5
HM100W-256	2	RT620B	100	RT625	256 Kb	50
HM110S-1024	1	RT620B	110	RT626	1 Mb	66
HM110D-256	2	RT620B	110	RT625	256 Kb	50
HM110D-1024	2	RT620B	110	RT626	1 Mb	66	8
HM125S-256	1	RT620B	125	RT625	256 Kb	50	6
HM125S-512	1	RT620C	125	RT626	512 Kb	66
HM125S-1024	1	RT620C	125	RT626	1 Mb	66	8
HM125D-256	2	RT620B	125	RT625	256 Kb	50
HM125D-512	2	RT620C	125	RT626	512 Kb	66
HM125D-1024	2	RT620C	125	RT626	1 Mb	66	8
HM133S-512	1	RT620C	133	RT626	512 Kb	66
HM133D-512	2	RT620C	133	RT626	512 Kb	66
HM133W-512	2	RT620C	133	RT626	512 Kb	66
HM142S-256	1	RT620C	142	RT626?	256 Kb	66?	15
HM142S-1024	1	RT620C	142	RT626	1 Mb	66
HM142W-1024	2	RT620C	142	RT626	1 Mb	66
HM150S-256	1	RT620B	150	RT625	256 Kb	50	9
HM150S-512	1	RT620C	150	RT626	512 Kb	66	7
HM150D-512	2	RT620C	150	RT626	512 Kb	66	10
HM150W-512	2	RT620C	150	RT626	512 Kb	66	12
HM166S-512	1	RT620C	166	RT626	512 Kb	66	11
HM180S-512 ("180MHz modules")	1	RT620D	180	RT626	512 Kb	50	13, 14
HM180D-512 ("dual 180MHz modules")	2	RT620D	180	RT626	512 Kb	50	13, 14
HMx4.5S-512 (sold as "180MHz modules")	1	RT620D	4.5 x MBus frequency	RT626	512 Kb	40	13, 14
HMx4.5D-512 (sold as "dual 180MHz modules")	2	RT620D	4.5 x MBus frequency	RT626	512 Kb	40	1, 13, 14
HMx4S-512 (sold as "200MHz modules")	1	RT620D	4 x MBus frequency	RT626	512 Kb	50	13
HMx4W-512 (sold as "dual 200MHz modules")	2	RT620D	4 x MBus frequency	RT626	512 Kb	50	13, 17
HMx4D-512 (sold as "dual 200MHz modules")	2	RT620D	4 x MBus frequency	RT626	512 Kb	50	13, 17

Footnotes:

1.

Rumoured to exist, but not yet confirmed.

2.

Although some HyperSPARC modules were rated suitable for MBus speeds upto 66MHz and beyond, very few actual MBus implementations were reliable above 50MHz. See High-Speed MBus Implementations.

3.

Internal Ross prototypes; never shipped. These single-width modules were approximately twice as long as standard MBus modules, at least in part to accomodate additional connectors for external logic probes: they were used to debug the RT625A and initial Ross OBP firmware, probably in a SPARCserver-630. As of 2001, it seems that only a single such module remainns in existance.

4.

Sold by Sun as the HS11.

5.

Sold by Sun as the HS12.

6.

Sold by Sun as the HS21.

7.

Sold by Sun as the HS151.

8.

A few early instances of these modules may have been double-width; post-1996 revisions are single-width.

9.

Might not exist: mentioned in some historical internal Sun documents, but maybe erroneously.

10.

Rare, only 100-150 units manufactured, of which approx 60 were only used internally by Ross in Germany.

11.

Rare.

12.

Rare, never available retail; only shipped to a few Ross "key customers".

13.

Half-speed level-2 cache.

14.

The original 180MHz modules (before Q4 1996) were discovered to have very occasional issues with the stability of the PLL clock-circuit in some systems, and were thus redesigned to have a bus-clock-multiplier circuit (x4.5) in place of the PLL. The bus-clocked 180MHz modules would only work on a 40MHz-or-slower MBus (of course!). After the HyperSPARC rights were bought by Bridgepoint (1998), a redesigned 180MHz PLL-clocked module became available. These later PLL-clocked 180MHz modules work fine on a 50MHz MBus, even though Bridgepoint still do not officially certify them for use in such systems.

15.

Unclear whether these modules use RT625 and/or RT626 cache-controllers.

16.

The RT620A-based HM90D modules can be distinguished from the RT620B-based flavour by the presence of onboard fans on the former.

17.

Dual-CPU "200MHz modules" from 1997-1998 are apparently all double-width (HMx4W-512); those manufactured from 2001 onwards are all single-width (HMx4D-512).

Relative Performance

The level-2 cache on HyperSPARC modules has a lower latency (zero-CPU-bus-wait-state load/store access for cache hits) than that that found on cached SuperSPARC modules.

However, the smaller level-1 instruction-cache (8Kb) on all HyperSPARC modules with RT620A/B/C CPUs favours the SuperSPARC (20Kb). HyperSPARC modules with RT620D CPUs have 16Kb of level-1 instruction-cache, which lessens the difference in those cases.

Also, the lack of a level-1 data cache on RT620A/B/C HyperSPARC CPUs incurs some performance penalty - even though level-2 cache hits do not incur wait-states, they still require an external CPU-bus cycle.

The MBus speed also matters: HyperSPARC modules and uncached SuperSPARC modules are capable of faster accesses to main memory than cached SuperSPARC modules, ie: a faster MBus speed favours HyperSPARC modules more than it does cached SuperSPARC modules.

And of course, the size of the level-2 cache really matters, especially for tasks involving intensive manipulation of large data-sets, or running programs that jump around outside the constraints of a level-1 instruction cache (eg: many Motif apps!).

There are also protocol differences in the HyperSPARC and cached SuperSPARC intra-module CPU-MMU buses, but I am not equipped to offer an opinion on the performance effects.

The CY7C601/2 CPUs are "previous generation" processor designs, although they do have a large, albeit external, level-1 cache (64Kb, unified).

Finally, SuperSPARC performance on XBus systems (eg: SPARCserver-1000) will differ from that on MBus systems, especially in multiprocessor configurations - the XBus has a higher latency but much higher bandwidth.

Summary: for general-purpose "desktop workstation" uses in single-processor MBus configurations, I would suggest that the relative performance, assuming the same CPU- and MBus-clock frequencies, is approximately:

eg: an HM100S-256 should have a similar feel to an SM61.

As always, your mileage may vary.

Note that the half-speed RT620D<->RT626 intra-module bus (on the RT620D-based HyperSPARC modules) penalises data-intensive workloads and workloads that do a lot of context-switching: for what I consider to be a typical workstation workload, with current (AD 2005) levels of context-switching, program size and dataset-sizes, a single HM180S-512 is only slightly quicker than an HM150S-512, and a pair of HM180S-512 modules performs the same as a pair of HM150S-512 modules. (the RT620D-based modules run quite a bit cooler, however).

For memory-intensive or thread-intensive workloads, or large programs (>20Mb "hot" text-segment), a 150MHz or 166MHz module will probably do better than a 180MHz or 200MHz one.

For memory-intensive workloads that seriously stress the capacity of the L2 cache (such as seti@home), 142MHz modules may be the best bet, especially on a 60/66MHz MBus.